Design & Implementation High Frequency Synchronous 16 X 16 Booth’s Multiplier on Spartan 3E using Customized DCM
This paper presents a modified design of Area-Efficient Low power 16x16 Booth’s Multiplier Circuit. In most of the digital circuit, clock is used as a input variable and clock is assigned during stimulation. Xilinx software is used to carry out all the design and implementation process.In this design a a single Digital clock manager(DCM) is used to generated a clock. In booth’s multiplier multiplication to two 16 bit number (multiplier and Multiplicand) is carried out using adders, multiplexer, inverter. Single DCM for high frequency operation.
Keywords - Single DCM, Xilinx, Adders, Multiplexers.cadence, utilization Factor.