Paper Title
Advancements In Clock Gating Techniques For Low-Power VLSI Circuit Design: A Systematic Literature Review

Abstract
The level of integration and circuit scale are augmented by the Integrated Circuit (IC) industry’s continuous advancement. Certainly, this condition results in a growth in power consumption by electronic devices, highlighting Low-Power (LP) technology’s growing significance in VLSI designs. A collection of techniques along with methodologies for minimizing the IC’s overall dynamic and static power consumption is termed LP design. Yet, power dissipation is one of the major issues that are faced. The product of total current and voltage loss in a circuit is a key constraint in LP Very Large Scale Integration (VLSI) design, especially when it comes to portable devices. Power dissipation must be carefully managed as device portability increases. This comprehensive review introduced the fundamental concept of LP and explored optimization measures by employing clock-gated circuits as a key example. Later, it summarizes the challenges along with prospects allied with LP technologies and mainly focuses on the advancements in Clock Gating (CG) techniques. These advancements in CG techniques provide the most prevalent as well as effective means to curtail power consumption via CG. Here, the elucidated techniques fulfill the power reduction objective, confirming that present along with future ICs remains highly efficient. This review outlines key advancements in CG methodologies that effectively reduce dynamic power consumption and support the development of scalable, energy-efficient VLSI systems for future applications. Keywords - Large-Scale Integration, Integrated Circuits, Clock Gating Techniques, Latch-Based Clock Gating, Data-Based Clock Gating, And Flip-Flop Clock Gating, Power-Optimization, Advanced Power Saving.