Paper Title
Low Power Multiplexer Using Stacking of Sleep Transistors

Abstract
The VLSI subsystems we use will have adders, multipliers and many combinational circuits. To design fast adders or multipliers we need complex adder architectures which need lot of multiplexers. These multiplexers need not to be enabled always. Multiplexers dissipate huge power in Integrated circuits when not used, due to leakage power. So, in this paper we tried to reduce the leakage power of multiplexers using stacking of sleep transistors. When two cutoff transistors are stacked over each other will reduce the leakage current almost to 50% compared to leakage current passing through a single cutoff transistor. So the sleep transistor here will contribute in reducing the leakage power almost to 50%. Keywords - Multiplexer, Low power, sleep transistor, leakage