Paper Title
FPGA based Smart Attendance Monitoring System

Abstract
The rapid proliferation of smart classrooms has created an immediate urge for secure, fast, and automated attendance systems to replace the relatively time-consuming and error-prone manual roll-calling or proxy attendance. This paper describes an FPGA-based Smart Attendance Monitoring System that integrates BLE, ESP32 wireless communication, and FPGA hardware logic for a secure, real-time, and tamper-resistant solution. Each student broadcasts a unique BLE advertisement consisting of a Roll Number and a Device Signature to ensure authenticity of identity and prevent spoofing of a device. ESP32 scans these broadcasts, extracts valid frames from them, and forwards them to the FPGA using an 8-bit parallel communicationprotocol. The proposed FPGA ensures registration validation, attendance marking, detection of duplicates, and actions related to unregistered IDs, updates a 16×2 LCD, and drives the LED indicators to show the present count. Realtime views of the students' registration, attendance, and session status can be displayed on web-based dashboards. The system is verified on behavioral simulation using ISim, Xilinx, and implemented on real hardware - Spartan-6 FPGA board coupled with the ESP32 module. The obtained results are presented, showing reliable performance with negligible latency and high robustness against proxy attendance; hence, it is suitable for smart-classrooms in modern times. Keywords - FPGA, attendance, Xilinx, simulation, BLE